FIG. 1 shows a circuit used in a prior art logic device such as manufactured by Xilinx, Inc, assignee of the present invention. I/O block 15 is a programmable input/output block which is connected through line 17 to an external pin of the integrated circuit chip, and which may be configured as an input buffer or an output buffer. Logic block 13 receives input signals on lines such as line 12, and generates an output signal on line 14. When I/O block 15 is configured as an output buffer, this output signal from line 14 is applied by I/O block 15 to an external pin. When I/O block 15 is configured as an input buffer, line 16 carries a signal from the pin to a universal interconnect matrix (UIM) 11. Alternatively, or in addition, the signal on line 14 may be fed back to UIM 11. Thus two lines, line 14 and line 16 are provided to connect the output of logic block 13 and the input and output of I/O block 15 to UIM 11. In a typical device, many pairs of logic block and I/O block will connect into the same UIM 11. For simplicity, only one additional pair of lines 33 and 37 is shown in FIG. 1.
At intersections of UIM 11 are programmable interconnectors such as interconnector 18. FIG. 2 shows the structure of interconnector 18. If EPROM transistor 19 has been programmed to form a connection, a high signal on line 14 may turn on EPROM transistor 19 so that voltage on line 12c is pulled low. A pullup resistor 20 connects line 12c to VCC so that if no lines such as lines 14 and 16 pull down line 12c, line 12c is pulled high. Thus line 12c provides the AND function of lines 14 and 16 and other lines which connect to line 12c. Each intersection in UIM 11 comprises a circuit such as circuit 18 shown in FIG. 2. In embodiments having many lines such as 14 and 16 entering UIM 11, very wide AND functions can be generated.
It is desirable to be able to generate additional functions such as NAND, NOR, and OR using UIM 11.
Further, with design rules becoming smaller and integrated circuit devices becoming more highly integrated, lines such as lines 14 and 16 can occupy considerable area in the chip. Thus it is desirable to minimize the number of lines needed to provide the necessary interconnections, and to maximize the usefulness of each line.